1. Field
The various circuit embodiments described herein relate in general to clock alignment between two clocks used in interfacing circuitry, and, more specifically, to apparatus and method for clock alignment for high speed interfaces.
2. Background
Alignment and matching of clocks serving two circuits that interface with synchronization is an important concern. As illustration of this concern, FIG. 1 shows a clock signal (CLK) from a timing circuit 102 (e.g., a Phase-locked loop (PLL)) that may reach different circuit blocks 104 and 106 at different times. If the two blocks 104 and 106 are interfacing or communicating with each other, data from one block (104) to another block (106) can be asynchronous due to mismatch of clock inputs resultant from different routing path delays. When circuit blocks are operated at lower frequencies, alignment of different clock signals can be accomplished by proper physical design, such as by designing placement and routing of clock signal runs to the circuitry have roughly equivalent transmission times to mitigate signal delays and skew between clock signals arriving at the circuitry. At circuitry operating at higher frequencies where skews are significant with respect to the clock period, however, malfunctioning may occur with disparate clock signals. Moreover, alignment in high speed circuits, such as in System on a Chip packages (SOC's) that run at Gigahertz (Ghz) frequencies, introduces difficult challenges resulting from significant skewing at higher frequencies that are not easily overcome by using a physical design approach to align clock signals.
Other than physical design, another approach to the problem of high speed circuits synchronization is to use Phase-locked loops (PLL's) to attempt to de-skew the clocks. A problem with such an approach, however, is that this solution requires larger size or chip area and consumes more power, which is of particular concern in SOC's, as well as necessitating special requirements in the physical layout of a chip. Additionally, the PLL approach generally does not afford availability to access its accurate functional model or change its functional model.